module trigger (
    input  clk,
    input  rst_n,
    input  start,
    output trg
);

    reg state1;
    reg state2;

    always @(posedge clk or negedge rst_n) begin
        if (!rst_n) begin
            state1 <= 1'b0;
            state2 <= 1'b0;
        end else begin
            state2 <= state1;
            state1 <= start; 
        end
    end

    // 0 => 1
    assign trg = (state2 == 0 && state1 == 1);

    //    0 1 1 0 0 0 
    // 1: 0 0 1 1 0 0 0 
    // 2: 0 0 0 1 1 0 0 0 
    // t: 0 0 1 

endmodule